View CY7C341B_186027.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

USE ULTRA37000TM FOR ALL NEW DESIGNS
CY7C341B
192-Macrocell MAX(R) EPLD
Features
* 192 macrocells in 12 logic array blocks (LABs) * Eight dedicated inputs, 64 bidirectional I/O pins * Advanced 0.65-micron CMOS technology to increase performance * Programmable interconnect array * 384 expander product terms * Available in 84-pin HLCC, PLCC, and PGA packages macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341B allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341B reduces board space, part count, and increases system reliability. Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and eight are buried, while for LABs B, C, D, E, H, I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell.
Functional Description
The CY7C341B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX(R) architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions. The 192 macrocells in the CY7C341B are divided into 12 Logic Array Blocks (LABs), 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the
Selection Guide
7C341B-25 Maximum Access Time 25 7C341B-35 35 Unit ns
Cypress Semiconductor Corporation Document #: 38-03016 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 22, 2004
USE ULTRA37000TM FOR ALL NEW DESIGNS
1 (A6) INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT (C6) 84 (C7) 83 (L7) 44 (J7) 43
CY7C341B
Logic Block Diagram
2 (A5) 41 (K6) 42 (J6)
SYSTEMCLOCK 4 (C5) 5 (A4) 6 (B4) 7 (A3) 8 (A2) 9 (B3) 10 (A1) 11 (B2) LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9-16 LAB B 12 13 14 15 (C2) (B1) (C1) (D2) MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21-32 LAB G MACROCELL 97 MACROCELL 98 MACROCELL 99 MACROCELL 100 MACROCELL 101 MACROCELL 102 MACROCELL 103 MACROCELL 104 MACROCELL 105-112 LAB H MACROCELL 113 MACROCELL 114 MACROCELL 115 MACROCELL 116 MACROCELL 117-128 54 55 56 57 (J10) (K11) (J11) (H10)
46 47 48 49 50 51 52 53
(L6) (L8) (K8) (L9) (L10) (K9) (L11) (K10)
16 (D1) 17 (E3) 20 (F2) 21 (F3)
LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36
P I A
LAB I MACROCELL 129 MACROCELL 130 MACROCELL 131 MACROCELL 132
58 59 62 63
(H11) (F10) (G9) (F9)
MACROCELL 37-48
MACROCELL 133-144
22 (G3) 23 (G1) 25 (F1) 26 (H1)
LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52
LAB J MACROCELL 145 MACROCELL 146 MACROCELL 147 MACROCELL 148
64 65 67 68
(F11) (E11) (E9) (D11)
MACROCELL 53-64
MACROCELL 149-160
27 (H2) 28 (J1) 29 (K1) 30 (J2)
LAB E MACROCELL 65 MACROCELL 66 MACROCELL 67 MACROCELL 68
LAB K MACROCELL 161 MACROCELL 162 MACROCELL 163 MACROCELL 164
69 70 71 72
(D10) (C11) (B11) (C10)
MACROCELL 69-80
MACROCELL 165-176
31 32 33 34 35 36 37 38
(L1) (K2) (K3) (L2) (L3) (K4) (L4) (J5)
LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELL 89-96
LAB L MACROCELL 177 MACROCELL 178 MACROCELL 179 MACROCELL 180 MACROCELL 181 MACROCELL 182 MACROCELL 183 MACROCELL 184 MACROCELL 185-192 VCC GND
73 74 75 76 77 78 79 80
(A11) (B10) (B9) (A10) (A9) (B8) (A8) (B6)
3, 24, 45, 66 (B5, G2, K7, E10) 18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
() - PERTAIN TO 84-PIN PGA PACKAGE
Document #: 38-03016 Rev. *C
Page 2 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Pin Configurations
PLCC/HLCC Top View
INPUT/CLK INPUT INPUT INPUT L GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
CY7C341B
PGA Bottom View
GND I/O INPUT I/O I/O I/O I/O
I/O I/O VCC
I/O I/O
I/O
I/O I/O
I/O
K 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 7C341B 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INPUT INPUT INPUT INPUT VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O J
I/O
I/O
I/O
I/O
GND
INPUT
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT INPUT
I/O
I/O
H
I/O
I/O
I/O
I/O
G
I/O
VCC
I/O 7C341B
I/O
GND
GND
F
I/O
I/O
I/O
I/O
I/O
I/O
E
GND
GND
I/O
I/O
VCC
I/O
D
I/O
I/O
I/O
I/O
C
I/O
I/O
I/O
INPUT INPUT
I/O
I/O
B
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
A
I/O
I/O 2
I/O 3
I/O 4
INPUT/ INPUT CLK GND 5 6 7
I/O 8
I/O 9
I/O 10
I/O
1
11
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
REGISTER tCLR tPRE tRSU tRH tRD tCOMB tLATCH OUTPUT DELAY tOD tXZ tZX INPUT/ OUTPUT
INPUT
INPUT DELAY tIN
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC LOGIC ARRAY DELAY tFD I/O DELAY tIO
Figure 1. CY7C341B Internal Timing Model
Document #: 38-03016 Rev. *C
Page 3 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Logic Array Blocks
There are 12 logic array blocks in the CY7C341B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C341B provides eight dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow.
400
CY7C341B
logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Design Recommendations
For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 mF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.
Design Security
The CY7C341B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device. The CY7C341B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.
IO OUTPUT CURRENT (mA) TYPICAL
I CC ACTIVE (mA) Typ.
300
VCC = 5.0V Room Temp.
200
100
0 100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Typical ICC vs. fMAX Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal
250 IOL 200 150 100 IOH 50 VCC = 5.0V Room Temp.
0
1
2
3
4
5
VO OUTPUTVOLTAGE (V)
Output Drive Current
Document #: 38-03016 Rev. *C
Page 4 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to +135C Ambient Temperature with Power Applied............................................. -65C to +135C Maximum Junction Temperature (Under Bias)................................................................. 150C
CY7C341B
Supply Voltage to Ground Potential[1].............. -2.0V to +7.0V DC Output Current, per Pin[1]..................... -25 mA to +25 mA DC Input Voltage[1]................................................-2.0V to +7.0V
Operating Range[3]
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 5% 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VCC VOH VOL VIH VIL IIX IOZ tR (Recommended) tF (Recommended) Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Input Rise Time Input Fall Time GND VIN VCC VO = VCC or GND Test Conditions Maximum VCC rise time is 10 ms VCC = Min., IOH = -4.0 mA[2] VCC = Min., IOL = 8 mA[2] 2.0 -0.3 -10 -40 Min. 4.75(4.5) 2.4 0.45 VCC+ 0.3 0.8 +10 +40 100 100 Max. 5.25(5.5) Unit V V V V V A A ns ns
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 20 Unit pF pF
AC Test Loads and Waveforms
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 250 R1 464 5V OUTPUT 5 pF R2 250 R1 464 3.0V GND < 6 ns tR tF ALL INPUT PULSES 90% 10% 90% 10% < 6 ns
(b)
THEVENIN EQUIVALENT (commercial/military) 163 OUTPUT 1.75V
Notes: 1. Minimum DC input is -0.3V. During transactions, input may undershoot to -2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. 3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-03016 Rev. *C
Page 5 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Switching Characteristics Over the Operating Range
7C341B-25 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tACO1 tAS1 tAH tAWH tAWL tCNT tODH fCNT tACNT fACNT Description Dedicated Input to Combinatorial Output Delay I/O Input to Combinatorial Output Delay[4] Global Clock Set-up Time Synchronous Clock Input to Output Delay[4] Input Hold Time from Synchronous Clock Input Synchronous Clock Input High Time Synchronous Clock Input Low Time Maximum Register Toggle Frequency[5] Dedicated Input or Feedback Set-up Time to Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Frequency[7] Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency[7] Time[6] Asynchronous Clock Input LOW Time[6]
[4]
CY7C341B
7C341B-35 Min. Max. 35 55 25 14 0 8 8 62.5 25 5 6 11 9 20 2 50 20 50 33.3 2 33.3 30 10 10 16 14 30 0 12.5 12.5 40.0 35 20 Unit ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz ns MHz
Min. Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial 15
Max. 25 40
Dedicated Asynchronous Clock Input to Output Delay[4] Commercial
Internal Switching Characteristics Over the Operating Range
7C341B-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tIC tICS Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[4]
[8]
7C341B-35 Min. Max 11 11 20 14 13 6 13 13 12 8 Unit ns ns ns ns ns ns ns ns ns ns 4 2 4 16 1 ns ns ns ns ns
Min. Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial 6 4
Max 5 6 12 12 10 5 10 10
Output Buffer Enable Delay[4] Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay
3 1 3 14 3
Notes: 4. C1 = 35 pF. 5. The fMAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped. 7. This parameter is measured with a 16-bit counter programmed into each LAB. 8. C1 = 5 pF.
Document #: 38-03016 Rev. *C
Page 6 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Internal Switching Characteristics Over the Operating Range (continued)
7C341B-25 Parameter tFD tPRE tCLR tPIA Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Description Commercial Commercial Commercial Min. Max 1 5 5 14
CY7C341B
7C341B-35 Min. Max 2 7 7 20 Unit ns ns ns ns
Programmable Interconnect Array Delay Commercial
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
External Synchronous
tWH tWL
SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY
tSU
tH
tCO1
REGISTERED OUTPUTS
External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL
Document #: 38-03016 Rev. *C
Page 7 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Combinatorial
INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tIN
CY7C341B
LOGIC ARRAY OUTPUT
tCOMB
OUTPUT PIN
tOD
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tAWH tAWL tF
tIC
tRSU
tRH
Internal Synchronous
SYSTEM CL OCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY tICS
tRSU
tRH
Document #: 38-03016 Rev. *C
Page 8 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE tRD tOD
CY7C341B
Ordering Information
Speed (ns) 25 Ordering Code CY7C341B-25HC/HI CY7C341B-25JC/JI CY7C341B-25RC/RI 35 CY7C341B-35HC/HI CY7C341B-35JC/JI CY7C341B-35RC/RI Package Name H84 J83 R84 H84 J83 R84 Package Type 84-lead Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 84-lead Windowed Pin Grid Array 84-lead Windowed Leaded Chip Carrier 84-lead Plastic Leaded Chip Carrier 84-lead Windowed Pin Grid Array Commercial/Industrial Operating Range Commercial/Industrial
Document #: 38-03016 Rev. *C
Page 9 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
CY7C341B
51-80081-**
Document #: 38-03016 Rev. *C
Page 10 of 12
USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
CY7C341B
51-85006-*A
84-Lead Windowed Pin Grid Array R84
51-80026-*B
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03016 Rev. *C
Page 11 of 12
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000TM FOR ALL NEW DESIGNS
Document History Page
Document Title: CY7C341B 192-Macrocell MAX(R) EPLD Document Number: 38-03016 REV. ** *A *B *C ECN NO. 106316 113613 122227 213375 Issue Date 05/17/01 04/11/02 12/28/02 See ECN Orig. of Change SZV OOR RBI FSG Description of Change Change from ecn #: 38-00137 to 38-03016 PGA package diagram dimensions were updated
CY7C341B
Power-up requirements added to Operating Range Information Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03016 Rev. *C
Page 12 of 12

▲Up To Search▲

Price & Availability of CY7C341B

	To Download CY7C341B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .